1. Technical Field
The present invention generally relates to a semiconductor circuit, and more particularly, to a delay-locked loop (DLL) circuit and a delay-locked method using the same.
2. Related Art
A semiconductor device, such as semiconductor memory, operates in response to an external clock signal, that is, a clock signal supplied from a memory controller.
When an external clock signal is inputted to semiconductor memory, the external clock signal passes through a variety of internal circuits, such as an input buffer, a signal line, an output buffer, and a variety of logic circuits, and thus the phase of the external clock signal is shifted.
For this reason, the semiconductor memory can include a circuit for compensating for a shift in the phase of the external clock signal, that is, a DLL circuit.
The DLL circuit performs a phase correction operation so that the phase of the output signal of the semiconductor memory coincides with that of the external clock signal by compensating for the delay time of the external clock signal by the internal delay time of the semiconductor memory to which the DLL circuit is applied.
A conventional DLL circuit is designed to periodically perform the phase correction operation.
Here, the phase of the external clock signal can be shifted by the abnormal operation of an external system, that is, a memory controller, or a change in the operating environment of the semiconductor memory.
As described above, the conventional DLL circuit performs the phase correction operation in a predetermined cycle. If the phase of the external clock signal is shifted to a level in which the phase cannot be compensated for before a cycle where the phase correction operation is performed is reached, the conventional DLL circuit does not compensate for the shifted phase, leading to a phase correction fail.